module	BKP_TXFRM(
   input                         GTM_RESET,
   input                         GTM_CLK155M52,

   input                         TRSV_IN_TXCLK,
   output[15:0]                  TRSV_OUT_TXDATA,

   input[15:0]                   TXFRM_IN_TXDATA,
   input                         TXFRM_IN_TXFP,

   output[2:0]                   DEBUG_CNT8,
   output[8:0]                   DEBUG_CNT270,
   output[3:0]                   DEBUG_CNT9
   );


  assign DEBUG_CNT8 = fmcnt_cnt8;
  assign DEBUG_CNT270  = fmcnt_cnt270;
  assign DEBUG_CNT9 = fmcnt_cnt9;
//  +++++++++++++++++++++++++++++++++++ Section 0 : input frame control count generate  +++++++++++++++++++++++++++++++++++++++  //
wire                             fmcnt_input_fp;
wire[15:0]                       fmcnt_input_data;
reg[2:0]                         fmcnt_cnt8;
reg[8:0]                         fmcnt_cnt270;
reg[3:0]                         fmcnt_cnt9;
reg[15:0]                        fmcnt_output_data;
reg[2:0]                         fmcnt_output_cnt8;
reg[8:0]                         fmcnt_output_cnt270;
reg[3:0]                         fmcnt_output_cnt9;
  assign fmcnt_input_fp          = TXFRM_IN_TXFP;
  assign fmcnt_input_data[15:0]  = TXFRM_IN_TXDATA[15:0];

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 )
      fmcnt_cnt8[2:0]                           <= 3'd0;
   else begin
      if ( fmcnt_input_fp==1'b1 )
         fmcnt_cnt8[2:0]                        <= 3'd1;
      else
         fmcnt_cnt8[2:0]                        <= fmcnt_cnt8[2:0]+3'd1;
   end
end
always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 )
      fmcnt_cnt270[8:0]                         <= 9'd0;
   else begin
      if ( fmcnt_input_fp==1'b1 )
         fmcnt_cnt270[8:0]                      <= 9'd0;
      else if ( fmcnt_cnt8[2:0]==3'd7 )begin
         if ( fmcnt_cnt270[8:0]==9'd269 )
            fmcnt_cnt270[8:0]                   <= 9'd0;
         else
            fmcnt_cnt270[8:0]                   <= fmcnt_cnt270[8:0]+9'd1;
      end
   end
end
always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 )
      fmcnt_cnt9[3:0]                           <= 4'd0;
   else begin
      if ( fmcnt_input_fp==1'b1 )
         fmcnt_cnt9[3:0]                        <= 4'd0;
      else if ( fmcnt_cnt8[2:0]==3'd7 && fmcnt_cnt270[8:0]==9'd269 ) begin
         if ( fmcnt_cnt9[3:0]==4'd8 )
            fmcnt_cnt9[3:0]                     <= 4'd0;
         else
            fmcnt_cnt9[3:0]                     <= fmcnt_cnt9[3:0] +4'd1;
      end
   end
end

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 ) begin
      fmcnt_output_data[15:0]                   <= 16'd0;
      fmcnt_output_cnt8[2:0]                    <= 3'd0;
      fmcnt_output_cnt270[8:0]                  <= 9'd0;
      fmcnt_output_cnt9[3:0]                    <= 4'd0;
   end
   else begin
      fmcnt_output_data[15:0]                   <= fmcnt_input_data[15:0];
      fmcnt_output_cnt8[2:0]                    <= fmcnt_cnt8[2:0];
      fmcnt_output_cnt270[8:0]                  <= fmcnt_cnt270[8:0];
      fmcnt_output_cnt9[3:0]                    <= fmcnt_cnt9[3:0];
   end
end




//  +++++++++++++++++++++++++++++++++++ Section 0 : overhead bytes insert  +++++++++++++++++++++++++++++++++++++++  //
wire[15:0]                       ovins_input_data;
wire[2:0]                        ovins_input_cnt8;
wire[8:0]                        ovins_input_cnt270;
wire[3:0]                        ovins_input_cnt9;
reg[15:0]                        ovins_output_data;
reg[2:0]                         ovins_output_cnt8;
reg[8:0]                         ovins_output_cnt270;
reg[3:0]                         ovins_output_cnt9;

  assign ovins_input_data[15:0]  = fmcnt_output_data[15:0];
  assign ovins_input_cnt8[2:0]   = fmcnt_output_cnt8[2:0];
  assign ovins_input_cnt270[8:0] = fmcnt_output_cnt270[8:0];
  assign ovins_input_cnt9[3:0]   = fmcnt_output_cnt9[3:0];
always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 ) begin
      ovins_output_data[15:0]                   <= 16'd0;
      ovins_output_cnt8[2:0]                    <= 3'd0;
      ovins_output_cnt270[8:0]                  <= 9'd0;
      ovins_output_cnt9[3:0]                    <= 4'd0;
   end
   else begin
      ovins_output_data[15:0]                   <= ovins_input_data[15:0];
      ovins_output_cnt8[2:0]                    <= ovins_input_cnt8[2:0];
      ovins_output_cnt270[8:0]                  <= ovins_input_cnt270[8:0];
      ovins_output_cnt9[3:0]                    <= ovins_input_cnt9[3:0];
   end
end



//  +++++++++++++++++++++++++++++++++++ Section 0 : input frame control count generate  +++++++++++++++++++++++++++++++++++++++  //
wire[15:0]                        b1fs_input_data;
wire[2:0]                         b1fs_input_cnt8;
wire[8:0]                         b1fs_input_cnt270;
wire[3:0]                         b1fs_input_cnt9;
reg[7:0]                          b1fs_b1_ins;
reg[7:0]                          b1fs_b1_calculating;
reg[15:0]                         b1fs_scram_vector;
reg[15:0]                         b1fs_output_data;
reg[2:0]                          b1fs_output_cnt8;
reg[8:0]                          b1fs_output_cnt270;
reg[3:0]                          b1fs_output_cnt9;

  assign b1fs_input_data[15:0]      = ovins_output_data[15:0];
  assign b1fs_input_cnt8[2:0]       = ovins_output_cnt8[2:0];
  assign b1fs_input_cnt270[8:0]     = ovins_output_cnt270[8:0];
  assign b1fs_input_cnt9[3:0]       = ovins_output_cnt9[3:0];

//assign TRSV_OUT_TXDATA[15:0]           = b1fs_output_data[15:0];

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 )
      b1fs_scram_vector[15:0]                   <= 16'd0;
   else begin
      if ( b1fs_input_cnt9[3:0]==4'd0 &&  b1fs_input_cnt270[8:0]==9'd8 && b1fs_input_cnt8[2:0]==3'd7)
         b1fs_scram_vector[15:0]                <= 16'hfe04;
      else begin
         b1fs_scram_vector[15]                  <= b1fs_scram_vector[6] ^ b1fs_scram_vector[5];
         b1fs_scram_vector[14]                  <= b1fs_scram_vector[5] ^ b1fs_scram_vector[4];
         b1fs_scram_vector[13]                  <= b1fs_scram_vector[4] ^ b1fs_scram_vector[3];
         b1fs_scram_vector[12]                  <= b1fs_scram_vector[3] ^ b1fs_scram_vector[2];
         b1fs_scram_vector[11]                  <= b1fs_scram_vector[2] ^ b1fs_scram_vector[1];
         b1fs_scram_vector[10]                  <= b1fs_scram_vector[1] ^ b1fs_scram_vector[0];
         b1fs_scram_vector[9]                   <= b1fs_scram_vector[0] ^ b1fs_scram_vector[6] ^ b1fs_scram_vector[5];
         b1fs_scram_vector[8]                   <= b1fs_scram_vector[6] ^ b1fs_scram_vector[4];
         b1fs_scram_vector[7]                   <= b1fs_scram_vector[5] ^ b1fs_scram_vector[3];
         b1fs_scram_vector[6]                   <= b1fs_scram_vector[4] ^ b1fs_scram_vector[2];
         b1fs_scram_vector[5]                   <= b1fs_scram_vector[3] ^ b1fs_scram_vector[1];
         b1fs_scram_vector[4]                   <= b1fs_scram_vector[2] ^ b1fs_scram_vector[0];
         b1fs_scram_vector[3]                   <= b1fs_scram_vector[1] ^ b1fs_scram_vector[6] ^ b1fs_scram_vector[5];
         b1fs_scram_vector[2]                   <= b1fs_scram_vector[0] ^ b1fs_scram_vector[5] ^ b1fs_scram_vector[4];
         b1fs_scram_vector[1]                   <= b1fs_scram_vector[6] ^ b1fs_scram_vector[5] ^ b1fs_scram_vector[4] ^ b1fs_scram_vector[3];
         b1fs_scram_vector[0]                   <= b1fs_scram_vector[5] ^ b1fs_scram_vector[4] ^ b1fs_scram_vector[3] ^ b1fs_scram_vector[2];
      end
   end
end

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 ) begin
      b1fs_output_data[15:0]                    <= 16'd0;
      b1fs_output_cnt8[2:0]                     <= 3'd0;
      b1fs_output_cnt270[8:0]                   <= 9'd0;
      b1fs_output_cnt9[3:0]                     <= 4'd0;
   end
   else begin
      b1fs_output_cnt8[2:0]                     <= b1fs_input_cnt8[2:0];
      b1fs_output_cnt270[8:0]                   <= b1fs_input_cnt270[8:0];
      b1fs_output_cnt9[3:0]                     <= b1fs_input_cnt9[3:0];
      if ( b1fs_input_cnt9[3:0]==4'd0 &&  (b1fs_input_cnt270[8:0]==9'd0 || b1fs_input_cnt270[8:0]==9'd1 || b1fs_input_cnt270[8:0]==9'd2) )
         b1fs_output_data[15:0]                 <= 16'hf6f6;
      else if ( b1fs_input_cnt9[3:0]==4'd0 &&  (b1fs_input_cnt270[8:0]==9'd3 || b1fs_input_cnt270[8:0]==9'd4 || b1fs_input_cnt270[8:0]==9'd5) )
         b1fs_output_data[15:0]                 <= 16'h2828;
      else if ( b1fs_input_cnt9[3:0]==4'd0 &&  (b1fs_input_cnt270[8:0]==9'd6 || b1fs_input_cnt270[8:0]==9'd7 || b1fs_input_cnt270[8:0]==9'd8) )
         b1fs_output_data[15:0]                 <= 16'h5555;
      else if ( b1fs_input_cnt9[3:0]==4'd1 &&  b1fs_input_cnt270[8:0]==9'd0 && b1fs_input_cnt8[2:0]==3'd0)
         b1fs_output_data[15:0]                 <= {b1fs_b1_ins[7:0], 8'd0} ^ b1fs_scram_vector[15:0];
      else
         b1fs_output_data[15:0]                 <= b1fs_input_data[15:0] ^ b1fs_scram_vector[15:0];
   end
end

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 )
      b1fs_b1_calculating[7:0]                  <= 8'd0;
   else begin
      if ( b1fs_output_cnt9[3:0]==4'd7 && b1fs_output_cnt270[8:0]==9'd269 && b1fs_output_cnt8[2:0]==3'd7)
         b1fs_b1_calculating[7:0]               <= 8'd0;
      else begin
         b1fs_b1_calculating[7]                 <= (b1fs_output_data[7] ^ b1fs_output_data[15]) ^ b1fs_b1_calculating[7];
         b1fs_b1_calculating[6]                 <= (b1fs_output_data[6] ^ b1fs_output_data[14]) ^ b1fs_b1_calculating[6];
         b1fs_b1_calculating[5]                 <= (b1fs_output_data[5] ^ b1fs_output_data[13]) ^ b1fs_b1_calculating[5];
         b1fs_b1_calculating[4]                 <= (b1fs_output_data[4] ^ b1fs_output_data[12]) ^ b1fs_b1_calculating[4];
         b1fs_b1_calculating[3]                 <= (b1fs_output_data[3] ^ b1fs_output_data[11]) ^ b1fs_b1_calculating[3];
         b1fs_b1_calculating[2]                 <= (b1fs_output_data[2] ^ b1fs_output_data[10]) ^ b1fs_b1_calculating[2];
         b1fs_b1_calculating[1]                 <= (b1fs_output_data[1] ^ b1fs_output_data[9])  ^ b1fs_b1_calculating[1];
         b1fs_b1_calculating[0]                 <= (b1fs_output_data[0] ^ b1fs_output_data[8])  ^ b1fs_b1_calculating[0];
      end
   end
end
always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if ( GTM_RESET==1'b1 )
      b1fs_b1_ins[7:0]                          <= 8'd0;
   else begin
      if ( b1fs_output_cnt9[3:0]==4'd7 && b1fs_output_cnt270[8:0]==9'd269 && b1fs_output_cnt8[2:0]==3'd7) begin
         b1fs_b1_ins[7]                 <= (b1fs_output_data[7] ^ b1fs_output_data[15]) ^ b1fs_b1_calculating[7];
         b1fs_b1_ins[6]                 <= (b1fs_output_data[6] ^ b1fs_output_data[14]) ^ b1fs_b1_calculating[6];
         b1fs_b1_ins[5]                 <= (b1fs_output_data[5] ^ b1fs_output_data[13]) ^ b1fs_b1_calculating[5];
         b1fs_b1_ins[4]                 <= (b1fs_output_data[4] ^ b1fs_output_data[12]) ^ b1fs_b1_calculating[4];
         b1fs_b1_ins[3]                 <= (b1fs_output_data[3] ^ b1fs_output_data[11]) ^ b1fs_b1_calculating[3];
         b1fs_b1_ins[2]                 <= (b1fs_output_data[2] ^ b1fs_output_data[10]) ^ b1fs_b1_calculating[2];
         b1fs_b1_ins[1]                 <= (b1fs_output_data[1] ^ b1fs_output_data[9])  ^ b1fs_b1_calculating[1];
         b1fs_b1_ins[0]                 <= (b1fs_output_data[0] ^ b1fs_output_data[8])  ^ b1fs_b1_calculating[0];
      end
   end
end



BKP_TXBUFF                           INST_BKP_TXBUFF(
   .GTM_RESET                        (GTM_RESET),
   .TXBUFF_IN_WR_CLK                 (GTM_CLK155M52),
   .TXBUFF_IN_WR_DATA                (b1fs_output_data[15:0]),
   .TXBUFF_IN_RD_CLK                 (TRSV_IN_TXCLK),
   .TXBUFF_OUT_RD_DATA               (TRSV_OUT_TXDATA[15:0])
   );


endmodule

